A memory device may include one or more memory banks. A memory bank typically includes multiple memory subarrays and multiple sense amplifiers. Additionally, a memory bank includes row decoders and column decoders to decode row and column addresses to access the data stored within the memory subarrays.
To improve memory performance or reduce power, memory devices have been developed that include multiple memory banks in a single device. The use of multiple memory banks in a single memory device increases performance by permitting simultaneous access to two or more different memory banks. An increased number of memory banks means fewer sense amplifiers per bank. This reduction in the number of sense amplifiers in each bank causes fewer sense amplifiers to be activated and fewer bit lines to be charged during a memory access, thereby reducing the power of the device. In existing memory devices, each memory bank is independent; i.e., each memory bank is capable of being operated and accessed separately from the other memory banks.
In any given memory core, the arrangement and orientation of the memory subarrays allows for a wide variety of memory bank organizations. Typically, additional memory banks cost die area. This die area penalty is caused by the additional row decoders and control circuits required to support each memory bank, and by the additional sense amplifier arrays for the memory subarrays to provide fully independent memory bank operation.
Memory core organizations can be classified into two broad categories: conventional organizations in which I/O wires are perpendicular to the bit lines, and hierarchical organizations in which the I/O wires are parallel to the bit lines.
FIG. 1 illustrates a die for a memory device having a conventional core architecture. Die 10 includes four independent memory banks 12, 14, 16, and 18 arranged as shown. Each memory bank 12-18 includes multiple arrays of sense amplifiers 20 shared between multiple memory subarrays 22. Memory subarrays 22 are arranged such that an array of sense amplifiers 20 is located on opposite sides of each memory subarray 22. Sense amplifiers 20 are used to determine the data stored in an adjacent memory subarray 22. Note that no sense amplifiers are shared between memory banks, although sense amplifiers are shared between memory subarrays within a particular memory bank.
To "open" a memory bank refers to the process of retrieving data from the memory cells to the sense amplifiers. Once the data has been retrieved from the memory cells into the sense amplifiers, the memory bank is "opened." To "close" a memory bank, data in the sense amplifiers is rewritten to the memory cells and the sense amplifiers are deactivated.
Each memory bank 12-18 includes row decoder and column control circuits for decoding the row addresses to access the data stored in memory subarrays 22. Additionally, column decoders 21 are located between each memory bank 12-18 and peripheral circuits 23. The row decoder activates a particular word line based on the received address. The column decoder selects one or more sense amplifiers from which data is retrieved based on the received address.
As illustrated in FIG. 1, each memory bank 12-18 is independent of the other memory banks; i.e., each memory bank is capable of being operated and accessed separately from the other memory banks. The arrays of sense amplifiers 20, row decoders, and column decoder circuits are associated with a specific memory bank. Because memory banks 12-18 are independent of one another, all four memory banks 12-18 can be accessed simultaneously.
Die 10 also includes a channel interface and input/output (I/O) pads 24, which are coupled to the pins or leads of the memory device. Additionally, peripheral circuits 23 are located on die 10. Peripheral circuits 23 include the circuits necessary to operate the memory device, such as voltage regulators and mechanisms for routing signals such as addresses, memory bank control signals, row sense signals, and memory bank open and close signals. Die 10 shown in FIG. 1 is provided for purposes of explanation, and is not necessarily drawn to scale.
As the number of memory banks in a memory device increases, the amount of support circuitry required increases and the die size (or die area) increases. In existing memory devices, each memory bank requires separate row decoders and other control circuits to support the memory bank. Additionally, each memory bank requires separate sense amplifiers to provide independent memory bank operation. Existing memory devices that have a small number of memory banks (e.g., 2 or 4 banks) do not require a significant increase in the number of sense amplifiers. However, as the number of memory banks increases (e.g., 8 or 16 banks), the additional area required by sense amplifiers becomes significant and increases die cost.